Various forms of photolithography have been employed in the making of mask openings or lines used in very large scale integrated circuit manufacture. Very small mask openings for emitter and other diffusion steps or very thin metallization patterns for chip device interconnections, for example, have been fabricated using resist materials selectively exposed by E-beam, X-ray or ion-beam irradiation through a photographically defined pattern.
More recently, a new technique has evolved to avoid the inherent optical limitations in the selective exposure of resist materials, as the mask opening size or width of the desired line patterns is reduced to the order of one micron or less for very high density integrated circuits. The new technique eliminates the use of photolithography to define the cited dimensions and substitutes a sidewall, reactive-ion etching (RIE) process whereby the dimensions are determined by the thickness of a deposited layer which can be controlled with great accuracy.
One example wherein a sidewall RIE process is used to define a narrow line pattern structure (in this case the length of an FET gate electrode) is given in U.S. Pat. No. 4,430,791, issued on Feb. 14, 1984 to Robert C. Dockerty and assigned to the present assignee. An example wherein a sidewall RIE process is used to define a small mask opening is given in U.S. Pat. No. 4,209,349, issued on June 24, 1980 to Irving T. Ho et al. and assigned to the present assignee. With respect to the latter example, however, a thermal oxidation step is employed after the formation of a silicon nitride sidewall. The thermal oxidation tends to produce the well-known "bird's beak" beneath the nitride sidewall which can impact the precision of control of the resulting emitter window width when the nitride is subsequently removed. It would be advantageous to avoid the use of process steps tending to produce a "bird's beak" whereby the benefit of mask opening control inherent in the sidewall RIE process could be fully exploited without loss.
U.S. Pat. No. 4,274,909, issued on June 23, 1981 to K. Venkataraman et al. and assigned to the present assignee, teaches an alternative non-sidewall RIE process for making mask openings of the order of a micron or less. The process incorporates photoresist planarization and isotropic etching steps which are somewhat more difficult to control with precision than is the case with sidewall RIE.